1. Field of Invention
The present invention relates to the fabrication process of thin film transistors (abbreviated as TFT below). Further, in detail, the present invention relates to optimized technology for each thin film which comprises the thin film transistor.
2. Description of Related Art
In thin film transistors (TFT) that are used in applications such as active elements in liquid crystal displays, a top gate structure in which a gate insulator layer and gate electrode are formed on the top side of the channel region is often used. In the fabrication process for this type of TFT structure, after substrate 10A is prepared as shown in FIG. 25 (A), underlevel protection layer 11A is formed on the surface of substrate 10A as shown in FIG. 25(B), after which semiconductor layer 12A consisting of an intrinsic amorphous silicon film is formed over the entire surface of substrate 10A. Next, semiconductor layer 12A is crystallized through laser annealing as shown in FIG. 25(C). Next, as shown in FIG. 26(A), resist mask 22A with a fixed mask pattern is formed; and semiconductor layer 12A is patterned using photolithography. Next, as shown in FIG. 26(B), gate insulator layer 13A consisting of a silicon oxide film is formed on the surface of semiconductor layer 12A by means of CVD. Next, as shown in FIG. 26(C), after conducting layer 21A consisting of a tantalum or other thin film is formed over the entire surface of substrate 10A by a means such as sputtering; gate electrode 15A is formed by patterning conducting layer 21A using photolithography as is shown in FIG. 26(D). Next, impurity ions are introduced into semiconductor layer 12A while using gate electrode 15A as a mask. As a result, source and drain regions 16A which are self-aligned with respect to gate electrode 15A are formed in semiconductor layer 12A; and the region of semiconductor layer 12A in which impurities ions were not introduced forms channel region 17A. Next, as shown in FIG. 26(E), after interlevel insulation film 18A consisting of a silicon oxide film is formed, source and drain electrodes 20A which form conducting junctions to source and drain regions 16A through contact holes 19A are formed. In this manner, TFT 30A is formed on the surface of substrate 10A. In this type of fabrication process, in the prior art, substrate 10A is exposed to atmosphere after a single process step is completed.
In the fabrication process of the prior art, however, when substrate 10A is exposed to atmosphere following completion of the annealing treatment of semiconductor layer 12A, the surface of crystallized semiconductor layer 12A can be oxidized through reactions to gaseous species, contaminated by hydrocarbons from the resist, for example, or contaminated by other impurities. In such a case, if gate insulator layer 13A is formed on the surface of semiconductor layer 12A that has been oxidized or contaminated, there will be a problem because the condition of the interface between channel region 17A and gate insulator layer 13A will deteriorate; and the electrical characteristics, such as the on current and the threshold voltage, of TFT 30A will worsen. Also, if, prior to crystallization by laser irradiation or other means, a natural oxide forms on semiconductor layer 12A as a result of the exposure of substrate 12A to atmosphere, there will be a problem because oxygen atoms will be incorporated into semiconductor layer 10A, the electrical conductivity of semiconductor layer 10A will vary widely, and the electrical characteristics of TFT 30A such as on current will worsen.
As a method to avoid such problems, a TFT fabrication process in which the semiconductor layer is not exposed to atmosphere is presented in Japanese Unexamined Patent Application Heisei 7-99321. In the process described as Example 2 in the aforementioned document, after substrate 10B is prepared as shown in FIG. 27(A), a phosphorous-doped semiconductor layer is formed on the surface. The semiconductor layer is patterned to form semiconductor layer islands 25B as shown in FIG. 27(B). Next, substrate 10B is inserted into a TFT fabrication unit and semiconductor layer 12B consisting of an amorphous silicon film is formed in vacuum using CVD as shown in FIG. 27(C). Next, as shown in FIG. 27(D), substrate 10B is laser annealed under vacuum. As a result, except for the region which becomes channel 17B, semiconductor layer 12B is phosphorous doped and source and drain regions 16B are formed. Next, as shown in FIG. 27(E), gate insulator layer 13B is formed on substrate 10B in vacuum using CVD; and substrate 10B is then removed from the TFT processing apparatus. At this point, the surface of semiconductor layer 12B is already covered by gate insulator layer 13B.
After this, as shown in FIG. 27(F), following photolithographic patterning of gate insulator layer 13B and semiconductor layer 12B, contact holes 19B are formed as shown in FIG. 28(A). After conducting layer 21B consisting of aluminum or other material is formed over the entire surface, gate electrode 15B is formed through further photolithography as shown in FIG. 28(B). Next, following formation of interlevel insulation film 18B as shown in FIG. 28(C), contact holes 26B are formed as shown in FIG. 28(D). Following formation of a conducting layer such as aluminum over the entire surface, the conducting layer is patterned by photolithography as shown in FIG. 28(E), and source and drain electrodes 20B are formed.
In this method, however, semiconductor layer 12B and gate insulator layer 13B are patterned simultaneously as shown in FIG. 27(F). As a result, as shown in FIGS. 28(A) and (B), when gate electrode 15B is formed during the next process steps through the patterning of conducting layer 21B which has been formed over the entire surface of substrate 10B, conducting layer 21B remains on the side walls of source and drain regions 16B. This leads to frequent occurrences of shorting between the source and drain regions, or between the source-gate and drain-gate regions. Further, there is also a problem with shorting to other TFTs on substrate 10B. In other words, in the fabrication process of the prior art, there is a problem with noticeably low yields of TFTs.
Moreover, in the prior art, in the process step shown in FIG. 27(D), silicon oxide species formed on top of semiconductor layer 25B or impurities from the resist or other sources may be incorporated into the semiconductor layer (mostly into source and drain regions) during laser melting. These impurities produce defects in the semiconductor layer and give rise to increases in off leakage current and threshold voltage shifts. Additionally, the surface of substrate 10B prior to the formation of semiconductor layer 12B is contaminated by the photolithography step to produce the source and drain. These impurities are intermixed in channel region 17B during crystallization causing a decrease in semiconductor layer film quality. Accordingly, in this prior art, since not only is the on current limited by impurities from the substrate surface, but the off current also increases as a result of oxygen (silicon oxide species) and contamination in the source and drain regions, it is not possible to produce high quality thin film semiconductor devices with large on-off current ratios.
Further, in this prior art, because gate insulator layer 13B formed by CVD is used in the as-deposited condition, the gate insulator layer film quality is not good and is known to lead to problems such as low gate-source breakdown voltages. As a result, there are problems both with the TFT electrical characteristics being poor as well as the yield and reliability being low. Additionally, a further problem exists since, as shown in FIG. 27(D), only laser annealing is done for semiconductor layer 12B which was formed by CVD. The result is retention of large stresses in the semiconductor layer which leads to a decrease in transistor characteristics.
Consequently, the present invention aims to solve the various problems mentioned above. The objective is to perform all process steps from the starting substrate to covering the surface of the semiconductor layer with the gate insulator layer without exposing the substrate to atmosphere, and, by producing a clean semiconductor layer/gate insulator layer interface by preventing contamination of the semiconductor layer surface from resist impurities, as well as by striving for high quality production of the semiconductor layer or of both the semiconductor layer and the gate insulator layer, to provide a fabrication process for high-yield, high-reliability TFTs.
TFT fabrication processes are mainly classified into two groups known as the low temperature process and the high temperature process. In the low temperature process, the maximum process temperature which is achieved by the entire substrate for a period of a few minutes or longer is not greater than approximately 600xc2x0 C. whereas in the high temperature process, the maximum process temperature which is achieved by the entire substrate for a period of a few minutes or longer is not less than approximately 800xc2x0 C. In contrast to the low temperature process in which the gate insulator layer is formed by a method such as CVD or PVD, the gate insulator layer is formed by a method such as thermal oxidation or high temperature oxidation (HTO) in the high temperature process. Additionally, in the high temperature process, thermal processing at a temperature between approximately 700 and 1200xc2x0 C. for a period of a few minutes to a few hours may be performed as necessary. While Embodiments 1 through 4 as well as 7 and 8 of the present invention may be applicable for both the low and high temperature processes, the meaning of the formation of a clean semiconductor layer/gate insulator layer interface (MOS interface) at low temperature relates mainly to the low temperature process. Embodiments 5 and 6 of the present invention relate to the high temperature process.
[Embodiment 1]
The TFT fabrication process pertaining to Embodiment 1 is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere; a second process step, following completion of the first process step, which involves thermal processing of said first gate insulator layer and said semiconductor layer; a third process step, following completion of the second process step, which involves patterning of said first gate insulator layer and said semiconductor layer; and a fourth process step, following completion of the third process step, which involves hydrogenation of said substrate followed by formation of a second gate insulator layer on the surface of said first gate insulator layer.
In the first process step of the present invention, because the substrate is not exposed to atmosphere from the formation of the semiconductor layer to the formation of the gate insulator layer, there is no formation of a dirty, natural oxide on the surface of the crystallized semiconductor layer as a result of reactions with the air or dust. At the same time, because the first gate insulator layer is formed prior to patterning of the semiconductor layer, the resist mask is formed on the surface of the first gate insulator layer but not on the surface of the semiconductor layer. Consequently, there is absolutely no contamination of the interface between the channel region and the gate insulator layer arising from hydrocarbons from the resist or other sources of impurities; and it is possible to obtain an extremely clean, good MOS interface. As a result, the electrical characteristics of the TFT such as on current and threshold voltage are improved.
In the second process step, the first gate insulator layer and the crystallized semiconductor layer are thermally processed. Prior to this thermal processing, the semiconductor atoms in the semiconductor layer are slightly displaced from their normal lattice positions and residual stresses caused by the crystallization are significantly present. Such minute lattice deviations and residual stresses are corrected by the thermal processing of the second process step. Accordingly, not only does the second process step relieve internal stresses in the semiconductor layer arising during the first process step from crystallization by either laser irradiation, melt crystallization, or rapid thermal annealing, but it also simultaneously further crystallizes the semiconductor layer to yield more nearly perfect crystals. Small amorphous regions existing between grains are crystallized, and irregular grain boundaries are converted to coincidence boundaries. Coincidence boundaries have two-dimensional periodicity and since dangling bonds are recombined, there are no deep-level states in the band gap. As a result, the probability of electron or hole scattering at the coincidence boundaries is greatly reduced and electrically superior interfaces are formed. Further, microcrystallites are recrystallized and grow into large grains; and the grain boundary area decreases significantly. The stress relief, crystallization, coincidence boundary formation, and further recrystallization afforded by the thermal processing of the second process step allows the attainment of extremely high quality semiconductor layers.
The thermal processing of the second process step additionally creates high quality first gate insulator layers. The low density, unstable first gate insulator layers formed by a method such as CVD are densified by the thermal processing of the second process step. Additionally, following thermal processing, the semiconductor atoms in the silicon or other semiconductor bond stably to the oxygen atoms to produce a stable material. As shown in FIG. 29, the weak, unstable chemical bonds between silicon atoms and oxygen atoms occurring in oxide layers formed at low temperature by methods such as CVD and PVD are converted into strong, stable bonds through the thermal processing of the second process step. Further, as shown in the flat band of the oxide layer before and after thermal processing in FIG. 30, the trap states for electrons and holes in the forbidden band (band gap) of the first gate insulator layer decrease after thermal processing. As a result of the improved quality of the first gate insulator layer, the injection of electrons and holes into the insulator layer is drastically reduced, the deterioration during TFT use decreases, and the reliability of the TFTs increases significantly. Also, because injection of electrons and holes from the semiconductor layer drain terminal into the insulator is difficult and there is no degradation of the TFTs, short channel TFTs are possible. Finally, the withstand voltage also increases, and the TFT stability improves dramatically.
Here, thermal processing inside a furnace is also acceptable for the thermal processing treatment, but rapid thermal annealing is even more desirable. In contrast to furnace thermal processing which occurs at temperatures between approximately 400 and 600xc2x0 C. for times between approximately one and ten hours, temperatures of between approximately 700 and 1000xc2x0 C. and times on the order of 0.1 second to less than about one minute are used in RTA. Because RTA uses a high temperature as compared to furnace processing, the effects of thermal processing described above are further enhanced. Throughput (processing time for a single substrate) also improves dramatically.
In RTA, optical energy is first absorbed in the semiconductor layer and the temperature of the semiconductor layer increases. Next, the first gate insulator layer is heated by the semiconductor layer which is underneath it, the temperature of the gate insulator layer rises, and thermal processing of the semiconductor layer and the first gate insulator layer is finished. Normally, because the temperature rise in transparent substrates is small, if a semiconductor layer is being processed, only regions in which the semiconductor layer remains significantly will be heated; and it is not possible to uniformly thermal process the entire substrate. In the present invention disclosure, however, because the thermal processing of the second process step occurs prior to the patterning of the semiconductor layer and the gate insulator layer, it is possible to thermally process both layers uniformly over the entire substrate.
In the fourth process step, the first gate insulator layer is hydrogenated after which the second gate insulator layer is formed. The semiconductor layer and first gate insulator layer are adversely affected by the release of hydrogen contained within the thin films and at the MOS interface during heating in the thermal processing of the second process step. The adverse effects are compensated, however, by hydrogenation during the fourth process step. Additionally, because the second gate insulator layer is formed after the patterning of the first gate insulator layer and the semiconductor layer and covers the side walls of the semiconductor layer, shorts between the gate electrode and semiconductor layer, or between the source region and the drain region, or between elements do not occur. Therefore, by means of the present invention, the yield and reliability are high.
In the present invention, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or rapid thermal annealing. It is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere. It goes without saying that during crystallization of the semiconductor layer, the bonds between semiconductor atoms are broken and reformed. There are inevitably unpaired electrons (dangling bonds) following bond reformation. Broken bonds between semiconductor atoms and unpaired electrons are extremely active. Consequently, if oxygen or water, carbon monoxide or carbon dioxide, or dust come in contact with the semiconductor layer during this period, these species become incorporated into the semiconductor layer as impurities. When crystallization is performed in pure hydrogen or under a hydrogen-containing atmosphere of an inert gas such as helium, nitrogen, or argon, the chemically active electron pairs are terminated by hydrogen thereby avoiding the incorporation of impurities into the semiconductor layer as mentioned above. It is thus possible to obtain high purity, high quality crystalline semiconductor layers.
It is desirable to have an atmosphere composed of a reducing gas such as hydrogen or monosilane (SiH4) in argon as the atmosphere in which melt crystallization, such as that performed by laser irradiation, occurs. In melt crystallization, the semiconductor atoms are easily scattered or the semiconductor layer surface can roughen. Such phenomena are minimized by performing melt crystallization under an atmosphere containing relatively high atomic weight species such as argon. This is because the high atomic weight species carry out the role of forcing down the molten semiconductor layer surface. Additionally, the reducing gas such as hydrogen or silane diluted in argon terminates the chemically active species in the crystallization process to produce a high purity crystalline layer.
In the present invention, it is desirable to perform the aforementioned second process step in a hydrogen-containing atmosphere, an oxygen-containing atmosphere, or a water vapor-containing oxidizing atmosphere. If the heating is carried out in a hydrogen gas atmosphere, the dangling bonds in the semiconductor layer, the first gate insulator layer, or the MOS interface can be terminated. If thermal processing is carried out in an oxygen gas atmosphere, the unbonded silicon atoms in the first gate insulator layer are forced to bond to oxygen, and it is possible to improve the insulator layer. Performing the thermal processing in a water vapor-containing oxidizing atmosphere simultaneously increases the degree of oxidation of the oxide layer (the value of x in SiOx approaches 2) as is found in thermal processing under an oxygen atmosphere and also more effectively improves the Sixe2x80x94Oxe2x80x94Si chemical bonds as well as more effectively reduces the trap states in the insulator layer to again produce a quality first gate insulator layer.
[Embodiment 2]
The TFT fabrication process pertaining to Embodiment 2 of the present invention is characterized by a fabrication process which includes the crystallization of the semiconductor layer in the TFT fabrication process pertaining to Embodiment 1 of the present invention as described above, followed by hydrogenation of the semiconductor layer prior to formation of the first gate insulator layer. Accordingly, the TFT fabrication process pertaining to Embodiment 2 is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by hydrogenation of said substrate during which said substrate is not exposed to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere; a second process step, following completion of the first process step, which involves thermal processing of said first gate insulator layer and said semiconductor layer; a third process step, following completion of the second process step, which involves patterning of said first gate insulator layer and said semiconductor layer; and a fourth process step, following completion of the third process step, which involves hydrogenation of said substrate followed by formation of a second gate insulator layer on the surface of said first gate insulator layer.
With such a process in which hydrogenation is performed immediately following crystallization, it is possible to terminate and stabilize the chemically active surface and grain boundaries of the semiconductor layer. In the present invention, a natural oxide does not form on the semiconductor layer surface because the substrate is not exposed to atmosphere following crystallization. Consequently, uniform hydrogenation may be carried out without the effects of a natural oxide layer. Hydrogenation of semiconductor layers in the prior art has required long time periods of up to several hours because the diffusion of hydrogen in insulator layers is slow. In the present invention, however, direct hydrogenation of the semiconductor layer is possible so that the processing time can be reduced to somewhere between approximately 10 seconds and 5 minutes depending on the thickness and degree of crystallinity of the semiconductor layer. Despite the short hydrogenation times, the electrical conductivity of the semiconductor layer is remarkably stable with the result being an improvement in the electrical characteristics of the TFT as given by the on and off currents.
In this invention as well, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or solid phase crystallization such as rapid thermal annealing. For the reasons explained previously, it is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere.
In this invention as well, it is desirable to perform the aforementioned second process step in a hydrogen-containing atmosphere, an oxygen-containing atmosphere, or a water vapor-containing oxidizing atmosphere. The reasons are again as explained previously.
[Embodiment 3]
The TFT fabrication process pertaining to Embodiment 3 of the present invention is characterized by a fabrication process in which an oxygenation treatment is performed in addition to the hydrogenation treatment during the first process step of the TFT fabrication process pertaining to Embodiment 2 of the present invention as described above. Accordingly, the TFT fabrication process pertaining to Embodiment 3 of the present invention is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by hydrogenation and oxidation, performed consecutively in the sequence listed, of said substrate during which said substrate is not exposed to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere; a second process step, following completion of the first process step, which involves thermal processing of said first gate insulator layer and said semiconductor layer; a third process step, following completion of the second process step, which involves patterning of said first gate insulator layer and said semiconductor layer; and a fourth process step, following completion of the third process step, which involves hydrogenation of said substrate followed by formation of a second gate insulator layer on the surface of said first gate insulator layer.
The crystalline semiconductor layer contains both unsatisfied bonds which can be terminated by hydrogen and unsatisfied bonds which cannot be terminated by hydrogen. Those unsatisfied bonds which cannot be terminated by hydrogen are terminated by oxygen in this invention, and it is possible to obtain good semiconductor devices with steep subthreshold (transistor on/off properties) characteristics. This phenomenon is particularly effective for the MOS interface. If the effective oxidation is carried out, a thin, high quality oxide film of about 20 angstroms to 300 angstroms is easily formed on the semiconductor surface; and a clean MOS interface is obtained. The semiconductor layer with a chemically active surface also reacts quickly with oxygen, and the oxidation can be performed in a short time which ranges from approximately 10 seconds to approximately 5 minutes. The oxidation can be performed by methods such as oxygen plasma irradiation, water plasma irradiation, water-containing oxygen plasma irradiation, hydrogen peroxide (H2O2) plasma irradiation, hydrogen peroxide-containing oxygen plasma irradiation, and ozone (O3) irradiation.
In this invention as well, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or solid phase crystallization such as rapid thermal annealing. For the reasons explained previously, it is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere.
In this invention as well, it is desirable to perform the aforementioned second process step in a hydrogen-containing atmosphere, an oxygen-containing atmosphere, or a water vapor-containing oxidizing atmosphere. The reasons are again as explained previously.
[Embodiment 4]
The TFT fabrication process pertaining to Embodiment 4 of the present invention is characterized by a fabrication process in which the surface of the first gate insulator layer, which has been contaminated by the resist mask used during the patterning of the semiconductor layer, is cleaned. Accordingly, the TFT fabrication process pertaining to Embodiment 4 of the present invention is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere, a second process step, following completion of the first process step, which involves thermal processing of said first gate insulator layer and said semiconductor layer; a third process step, following completion of the second process step, which involves patterning of said first gate insulator layer and said semiconductor layer; a fourth process step, following completion of the third process step, which involves cleaning of the surface of said first gate insulator layer; and a fifth process step, immediately following completion of the fourth process step, which involves hydrogenation of said substrate followed by formation of a second gate insulator layer on the surface of said first gate insulator layer.
With such a process, although the surface of the first gate insulator layer is contaminated by the resist mask used during the patterning of the semiconductor layer and the first gate insulator layer, the contamination of the gate insulator layers is kept to a minimum because the contaminated portion is cleaned prior to formation of the second gate insulator layer. Consequently, the fixed charges in the gate insulator layer are reduced and the threshold voltages of the transistors are stabilized throughout the lots. Additionally, the variations in transistor properties are reduced even with respect to long term continuous use, and the transistor reliability is remarkably improved. Also, because the withstand voltage of the gate insulator layer increases, along with an improvement in reliability comes the possibility of reducing the thickness of the gate insulator layer. In the description of the second process step in the first embodiment of the present invention, it was explained that short channel TFTs are possible by means of the present invention. Combining this and the reduction in thickness of the gate insulator layer, it becomes possible to apply the scaling principle to TFT elements just as is done in LSI technology. By applying an LDD structure to the present invention, a submicron TFT with a channel length of approximately 0.5 to 1 xcexcm, and a gate insulator layer thickness of from approximately 100 angstroms to 300 angstroms can be realized.
The cleaning of the surface of the first gate insulator layer in the aforementioned fourth process step of the present invention includes etching of the first gate insulator layer by such techniques as wet etching by an aqueous solution containing hydrofluoric acid (HF) or dry etching by a hydrogen, CHF3, NF3, or SF6 plasma.
As a result, only the surface layer of the first gate insulator layer contaminated by the resist mask is removed and the semiconductor layer is also not exposed to atmosphere during this period since the clean, remaining first gate insulator layer protects the semiconductor layer. In such a fashion, because a clean MOS interface is preserved and it is possible to form the second gate insulator layer on top of a high quality first gate insulator layer, the electrical characteristics of the TFT are stabilized.
In this invention as well, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or rapid thermal annealing. For the reasons explained previously, it is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere.
In this invention as well, it is desirable to perform the aforementioned second process step in a hydrogen-containing atmosphere, an oxygen-containing atmosphere, or a water vapor-containing oxidizing atmosphere. The reasons are again as explained previously.
In the fabrication process of Embodiments 1 through 4 of the present invention, it is desirable to carry out all process steps including and after the formation of the second gate insulator layer at temperatures of no more than approximately 350xc2x0 C. By so doing, because the semiconductor layer and first gate insulator, which are hydrogenated just prior to formation of the second gate insulator layer, as well as the second gate insulator layer are not exposed to high temperatures, the hydrogen within these layers and at the interface is not expelled; and it is possible to avoid the degradation in TFT elements which accompanies such loss of hydrogen.
[Embodiment 5]
The TFT fabrication process pertaining to Embodiment 5 of the present invention is characterized by the use of a high temperature process. Accordingly, the TFT fabrication process pertaining to Embodiment 5 of the present invention is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere; a second process step, following completion of the first process step, which involves patterning of said first gate insulator layer and said semiconductor layer; and a third process step, following completion of the second process step, which involves thermal treatment of said substrate in an oxidizing environment and the formation on the surface of said semiconductor layer of an oxide layer as a second gate insulator layer.
In the first process step of the present invention as well, because the substrate is not exposed to atmosphere from the formation of the semiconductor layer to the formation of the gate insulator layer, there is no formation of a dirty, natural oxide on the surface of the crystallized semiconductor layer as a result of reactions with the air or dust. At the same time, because the first gate insulator layer is formed prior to patterning of the semiconductor layer, the resist mask is formed on the surface of the first gate insulator layer but not on the surface of the semiconductor layer. Consequently, following formation of the oxide layer on the surface of the semiconductor layer in the third process step there are absolutely no impurities such as carbon compounds in the gate insulator layer, and a high purity gate insulator layer is formed. As a result, the electrical characteristics of the TFT such as on current and threshold voltage are improved.
In the third process step of the present invention, because the formation of the oxide layer which acts as the second gate insulator layer on the semiconductor layer surface is carried out by thermal processing between approximately 900xc2x0 C. and 1200xc2x0 C., the semiconductor layer crystallized in the first process step is improved by means such as the release of stress. This means the progression of stress release, crystallization of grain boundaries, formation of coincidence boundaries, and recrystallization as explained with reference to the second process step in Embodiment 1 of the present invention. In Embodiment 5, the thermal processing occurs at higher temperatures and over a long time period such that the effects are increased dramatically. In Embodiment 5 of the present invention, it is possible to obtain an extremely good semiconductor layer since the film quality of the high quality semiconductor layer obtained in the first process step is further remarkably improved in the third process step. Further, because the film quality of the first gate insulator layer is improved through densification of the first gate insulator layer, for example, the reliability of TFTs so fabricated is high. The circumstances concerning these parts are the same as explained previously with respect to the second process step in Embodiment 1 of the present invention. Also, because the second gate insulator layer is formed through thermal oxidation following patterning of the first gate insulator layer and the semiconductor layer and completely covers the side walls of the semiconductor layer, the various types of shorts described previously do not occur in the present invention. As a result the yield and reliability from this invention are high.
In this invention as well, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or rapid thermal annealing. For the reasons explained previously, it is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere
[Embodiment 6]
The TFT fabrication process pertaining to Embodiment 6 of the present invention is characterized by a fabrication process which includes the first process step in the TFT fabrication process pertaining to Embodiment 5 of the present invention as described above, followed by thermal processing of the semiconductor layer and first gate insulator layer in the second process step. Accordingly, the TFT fabrication process pertaining to Embodiment 6 is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere; a second process step, following completion of the first process step, which involves thermal process of said first gate insulator layer and said semiconductor layer; a third process step, following completion of the second process step, which involves patterning of said first gate insulator layer and said semiconductor layer; and a fourth process step, following completion of the third process step, which involves thermal treatment of said semiconductor layer of an oxide layer as a second gate insulator layer.
In the present invention, the semiconductor layer improves in the same fashion as in the second process step of Embodiment 1 of the present invention since the first gate insulator and the semiconductor layer are thermally processed in the second process step here as well. Additionally, the reliability of TFTs fabricated using this procedure is high because the first gate insulator layer densifies during heating. The semiconductor and first gate insulator layers which have been improved in this fashion are further improved to produce higher quality films as a result of the thermal oxidation which occurs in the fourth process step. For the thermal processing in the second process step, thermal processing in a furnace is also acceptable, but rapid thermal processing allows higher temperatures such that the effects of thermal processing described previously can be increased further and it becomes possible to obtain other effects such as high throughput. In this case as well, because the rapid thermal processing is performed prior to patterning, the degree of thermal absorption is uniform across the entire substrate.
In this invention as well, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or rapid thermal annealing. For the reasons explained previously, it is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere.
In this invention as well, it is desirable to perform the aforementioned second process step in a hydrogen-containing atmosphere, an oxygen-containing atmosphere, or a water vapor-containing oxidizing atmosphere. The reasons are again as explained previously.
[Embodiment 7]
In each of the inventions described above, the gate insulator layer and the semiconductor layer are thermally processed following formation of the first gate insulator layer. In contrast, as in Embodiment 7 and 8 of the present invention, it is also possible to fabricate high quality semiconductor devices in a process in which the substrate is not exposed to atmosphere following formation of the semiconductor layer up to the formation of the first gate insulator layer, and, further, in which the semiconductor layer is hydrogenated or oxidized. As a result, TFTs with high yield and high reliability can be produced.
The TFT fabrication process pertaining to Embodiment 7 of the present invention is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by at least either hydrogenation or oxidation treatment of said substrate without exposing said substrate to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere; a second process step, following completion of the first process step, which involves patterning of said first gate insulator layer and said semiconductor layer; and a third process step, following completion of the second process step, which involves the formation of a second gate insulator layer on the surface of said first gate insulator layer.
In the present invention, a natural oxide does not form because the surface of the semiconductor layer is not exposed to atmosphere following crystallization. Consequently, during subsequent hydrogenation or oxidation, there are no effects from a natural oxide layer; and it is possible to uniformly and effectively effect hydrogenation or oxidation in a short time. The electrical conductivity of the semiconductor layer is stable and there is an improvement in the electrical characteristics of the TFT such as the on current. Also, because the first gate insulator layer is formed prior to patterning of the semiconductor layer, the resist mask is formed on the surface of the first gate insulator layer but not on the surface of the semiconductor layer. Consequently, there is no contamination of the semiconductor layer surface from the resist, and the interface condition between the channel region and the gate insulator layer is good. Additionally, because the formation of the second gate insulator layer follows the patterning of the first gate insulator layer and the semiconductor layer and covers the semiconductor side walls, there is also the advantage of none of the previously described shorts occurring.
In this invention as well, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or solid phase crystallization such as rapid thermal annealing. For the reasons explained previously, it is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere.
[Embodiment 8]
The TFT fabrication process pertaining to Embodiment 8 of the present invention is characterized by a fabrication process which includes at least a first process step which involves the formation of a semiconductor layer on a substrate which is isolated from atmosphere, followed by crystallization of said semiconductor layer in a non-oxidizing atmosphere without exposing said substrate to atmosphere, followed by at least either hydrogenation or oxidation treatment of said substrate without exposing said substrate to atmosphere, followed by formation of a first gate insulator layer on top of said semiconductor layer during which said substrate is not exposed to atmosphere; a second process step, following completion of the first process step, which involves patterning of said first gate insulator layer and said semiconductor layer; a third process step, following completion of the second process step, which involves cleaning the surface of the first gate insulator layer; and a fourth process step, following completion of the third process step, which involves the formation of a second gate insulator layer on the surface of said first gate insulator layer.
In Embodiment 8, the TFT electrical characteristics are stable because of the cleaning of the first gate insulator layer which is contaminated by the resist mask during patterning of the semiconductor layer. Here, only the surface layer of the first gate insulator layer is removed and striving for cleanliness, the semiconductor layer is not exposed to atmosphere. Consequently, because it is possible to absolutely prevent dirty oxides on the semiconductor surface, the TFT electrical characteristics are further stabilized.
The cleaning of the surface of the first gate insulator layer in the aforementioned third process step of the present invention includes etching of the first gate insulator layer by such techniques as wet etching by an aqueous solution containing hydrofluoric acid (HF) or dry etching by a hydrogen, CHF3, NF3, or SF6 plasma.
In this invention as well, the crystallization in the first process step is carried out by melt crystallization, by means such as laser irradiation for example, or solid phase crystallization such as rapid thermal annealing. For the reasons explained previously, it is desirable to perform such crystallization either in a hydrogen-containing atmosphere or a reducing, argon-containing atmosphere.